1. Field of the Invention
The invention relates generally to the field of electrostatic discharge (ESD) protection of semiconductor circuits. More particularly, in one embodiment, the invention relates to a low-voltage triggering (LT) N-channel metal oxide semiconductor (NMOS) that can turn on rapidly during an ESD event and provide a lower resistance, substantially uniform current density path for an ESD current, thereby effectively shunting substantially all of an ESD pulse.
2. Discussion of the Related Art
Prior art electrostatic discharge protection devices are known to those skilled in the art. For example, a conventional approach to providing electrostatic discharge protection is to provide a circuit with a device that can intervene to deflect a potentially dangerous electrostatic discharge towards ground, and away from the remaining components of the circuit, during an electrostatic discharge event.
One way to provide ESD protection is to use a thick field device. For example, referring to FIG. 1, a conventional thick field device (TFD) is shown where an N+doped source 110 and an N+doped drain 120 are located within a P doped well 130. Isolation oxides 140 are located next to the N+doped source 110 and the N+doped drain 120 at the top of the P doped well 130. There is no gate in the TFD illustrated in FIG. 1, and this TFD simply turns on by avalanche breakdown across the drain/channel junction. The TFD shown in FIG. 1 is a conventional approach to providing Vdd/Vss ESD protection.
Another way to provide ESD protection is to use a grounded gate thin oxide NMOS. For instance, referring to FIG. 2, a grounded gate thin oxide NMOS (GGNMOS) is shown where the N+doped source 110 and the N+doped drain 120 are located within the P doped well 130. A gate 210 is located above and between the N+doped source 110 and the N+doped drain 120. Two n-doped regions 220 are located beneath the gate 210. A first of the two n-doped regions 220 is located adjacent the N+doped source 110 and a second of the two n-doped regions 220 is located adjacent the N+doped drain 120. Two spacers 230 are located next to the gate 210. Isolation oxides 140 are located next to the N+doped source 110 and the N+doped drain 120 at the top of the P doped well 130. The device shown in FIG. 2 is a conventional LDD NMOS, with n-implantation, approach to providing Vdd/Vss ESD protection. Unfortunately, even the trigger voltage of the LDD NMOS device shown in FIG. 2 is not low enough to protect many types of circuitry from damage.
Thus, two ways to provide Vdd vs. Vss power bus protection are represented by the thick field device (TFD) shown in FIG. 1 and the grounded gate thin oxide NMOS (GGNMOS) shown in FIG. 2. Both of these protection devices operate as NPN bipolar devices during an ESD event. The I-V characteristic of these NPN bipolar devices is represented in FIG. 3. More specifically, trace shown in FIG. 3 represents the snapback I-V characteristics of the GGNMOS illustrated in FIG. 2. Referring to FIG. 3, when the voltage reaches a trigger voltage (Vtri), the NPN device turns on and enters into snapback region of low impedance (Vsp) so as to permit the dissipation of high amounts of ESD energy.
An ESD protection device (e.g., a power bus protection device) with a lower (Vtri) can effectively turn on more quickly (first) to protect internal circuitry from damage. Further, an ESD protection device with a lower snapback voltage (Vsp) can dissipate higher current and achieve a higher ESD threshold. A good ESD protection circuit must have both i) a lower trigger voltage (Vtri) and ii) a lower snapback voltage (Vsp).
However, the ESD protection performance available using these prior art approaches has degraded in association with advanced processes, such as, for example, lightly doped drain (LDD) devices, the use of thinner oxide layers, and the salicide process, etc. As these, and other, advanced processes evolve, more and more ESD damage is occurring in sub-micron integrated circuits during ESD pulse stress despite the use of the TFD and GGNMOS approaches.
The conventional TFD and GGNMOS approaches are not a good way to provide power bus ESD protection in the context of advanced processes, such as, for example, the above-mentioned lightly doped drain (LDD) devices, thinner oxide layers, and salicide process, etc. Specifically, the higher trigger voltage levels that are inherent to the conventional TFD and GGNMOS approaches cannot protect weaker circuits against ESD damage.
In particular, a drawback of using the conventional LDD device shown in FIG. 2 is that such devices are very weak during ESD stress. In more detail, the LDD n-region induces non-uniform current distribution and local hot spots. As device sizes shrink into the sub-micron regime and beyond, these hots spots become more problematic. Therefore, the LDD NMOS device shown in FIG. 2 cannot, by itself, act as a good ESD protection circuit.
One unsatisfactory approach, in an attempt to solve the above-discussed problem of nonuniform current distribution involves using a non-lightly doped drain (non-LDD) device. A non-LDD NMOS device is shown in FIG. 4. Referring to FIG. 4, again the N+doped source 110 and the N+doped drain 120 are located within the P doped well 130. The gate 210 is again located above and between the N+doped source 110 and the N+doped drain 120 and two spacers 230 are located next to the gate 210. Isolation oxides 140 are again located next to the N+doped source 110 and the N+doped drain 120 at the top of the P doped well 130. The difference between the structures shown in FIG. 2 and FIG. 4 is that the device shown in FIG. 4 has no n-doped regions. The absence of any n-doped regions obviates the hot spot problems inherent to the device shown in FIG. 2. The purpose of using such a non-LDD device was to improve the current distribution (compared to the device shown in FIG. 2), by making the current distribution more uniform. In the absence of n-doped regions, this limited purpose is achieved by the device shown in FIG. 4.
Unfortunately, the trigger voltage of the non-LDD device shown in FIG. 4 is not low enough to protect many types of circuitry from damage. The use of device shown in FIG. 4 in association with circuitry that is based on advanced processes, such as, for example, the above-mentioned lightly doped drain (LDD) devices, the use of thinner oxide layers, and the salicide process, etc., often results in damage from ESD stress due to the trigger voltage (Vtri) being inappropriately high.
Thus, one requirement of this technology has been that an ESD protection approach should be capable of switching on very quickly to protect the balance of the integrated circuit. Therefore, what is required is solution that has a low triggering voltage (Vtri), so as to exhibit a quick reaction time.
Another requirement of this technology has been that an ESD protection approach should be capable of conducting substantially all of an ESD pulse. Thus, what is also required is a solution that has a low snapback voltage (Vsp), so as to exhibit the ability to shunt substantially all of an ESD pulse.
Another requirement of this technology has been that such an ESD protection approach should be capable of conducting substantially all of an ESD pulse without developing any hot spots. Thus, what is also required is solution that has a uniform current distribution, so as to exhibit the ability to shunt substantially all of an ESD pulse.
Another requirement of this technology has been that such an ESD protection approach should be economical to implement. A disadvantage of the previous approaches represented in FIGS. 1-4 has been relatively high cost. Thus, what is also required is a solution that meets the above-discussed requirements in a more cost effective manner.
Therefore, what is needed to improve ESD protection performance is a low-voltage triggering protection approach that combines a low triggering voltage (Vtri) with a low snapback voltage (Vsp) and uniform current distribution, and is economical to fabricate in the context of a salicide integrated circuit. Heretofore, the requirements of low triggering voltage (Vtri), low snapback voltage (Vsp), uniform current distribution, and low cost referred to above have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.